From an XOR gate to an 8-bit address decoder
Digital logic design built up from a single gate to a working address decoder, verified in VHDL simulation.
- Year
- 2014
- Context
- Electronic engineering, Loughborough University
- Tools
- VHDL, CAE schematic capture, Waveform simulation
The aim
Learn digital design from the ground up, starting from a single gate and finishing with a component a real computer would use.
What we did
- Designed an XOR gate at schematic level in a computer-aided engineering (CAE) tool.
- Built it up into larger combinational blocks, ending with an 8-bit address decoder of the kind that maps a processor’s address bus to memory and peripherals.
- Wrote VHDL testbenches and verified each block with waveform simulation.
- Alongside the digital work, simulated a transistor amplifier circuit.
Why it matters
Everything we build now, from cloud platforms to AI models, runs on this layer. Knowing how it works helps when performance, cost or reliability come down to the hardware.